Faced with an inevitable slow-down of Moore’s Law progress, silicon vendors are turning to chip architecture innovation as a way to reduce the cost and complexity of creating increasingly powerful processors for emerging AI, Cloud, Edge, HPC, and graphics applications.
One new chip design methodology, called “chiplets,” adopts a building-block approach to SoC design, whereby multiple pre-designed (and pre-tested) function blocks are combined to create a new SoC design. The approach offers far superior component price/performance ratios, along with reduced development costs and timelines, by leveraging pre-existing chiplet function blocks.
Many major semiconductor companies are in the process of migrating to chiplet-based designs, spurred on by the Open Compute Project (OCP), which launched a decade ago. OCP’s chiplet concept emerged from a Facebook SoC design, and gained traction and support from Goldman Sachs, Rackspace, Intel, and Sun co-founder and chip guru Andy Bechtolsheim. The OCP community was founded with a focus on “redesigning hardware technology to efficiently support the growing demands on compute infrastructure,” and made its mark in Facebook’s datacenter, which was lauded as “38 percent more energy efficient to build and 24 percent less expensive to run than the company’s prior facilities.”
DARPA, which has an active interest in boosting the U.S. semiconductor industry, is in the process or creating a large catalog of third-party chiplets for use in both commercial and military applications. DARPA expects its “CHIPS” (Common Heterogeneous Integration and IP Reuse Strategies) initiative to yield a 70 percent reduction in the cost of designing complex chips.
NVIDIA, Intel, Marvell, and AMD are all currently engaged in chiplet-based GPU designs. In particular, last week AMD announced a unique, patented [PDF download] chiplet design approach that uses a new, high-bandwidth interconnect mechanism for communication among chiplets, making the design appear to be a single big, monolithic GPU.
Two figures from AMD’s chiplet-related patent
(click images to enlarge)
A recent EETimes report quotes Intel’s Intel’s “IC packaging mavin,” Ramune Nagisetty, as characterizing chiplets as an “inflection point [in] the rise of disruptive AI architectures based on neural networks,” and pointed to the ImageNet competition in 2012 that has given rise to packaging innovation. According to a Nov. 2018 Wired report, Nagisetty associated the advent of chiplets with the continued evolution of Moore’s Law.
(Lego image credit: “Photo by Alan Chia – Lego Color Bricks — CC BY-SA 2.0 – via https://commons.wikimedia.org/w/index.php?curid=6068229)