RISC-V: the Linux of chips

A recently released study from the Wilson Research Group reports that nearly a quarter of ASIC and FPGA chip designs during 2020 tapped open-source RISC-V technology, flagging it as one of the top trends in compute.

Specifically, the Wilson Research Group/Siemens “Functional Verification” study, reported that 23 percent of chip projects during 2020, “in both the ASIC and FPGA spaces, incorporated at least one RISC-V processor.”

RISC-V interest by application and geographic region
(click images to enlarge; source)

RISC-V has been shaking up the semiconductor industry recently, with companies increasingly designing their own custom RISC-V ISA-based chips. This trend made news again this week as MIPS Technologies — a pioneer in Reduced Instruction Set Computer (RISC) architecture processor technology with its MIPS processors — emerged from Chapter 11 bankruptcy (along with its parent, Wave Computing Inc.), rebranded itself as “MIPS,” and declared its intention to become a leader in RISC-V processors. In a March 1 news release, MIPS said it will be focused on “developing a new industry-leading standards-based 8th generation architecture, which will be based on the open source RISC-V processor standard.”

A report from Semico Research predicts that the compute market “will consume 62.4 billion RISC-V CPU cores by 2025, a 146% CAGR from 2018.” The biggest share is predicted to be industrial, with 17 billion cores. Furthermore, research released last month forecasts “that the compound annual growth rate for RISC-V cores between 2020 and 2025 will approach 115%.” Semico noted that the fastest growing served available market for RISC-V “is automotive which is projected to achieve a 274.3% CAGR.”

Like many other Open Source technologies (e.g. Unix), MIPS got its start as a UC Berkeley Research Project in 2010 and has since spawned an ecosystem from developers to governments to businesses all over the world. Like other significant architectures before it, the project was funded by government and commercial organizations including Defense Advanced Research Projects Agency (DARPA), Semiconductor Research Corporation, Intel, Google, Nokia, NVIDIA, Oracle, and Samsung.

The RISC-V instruction set architecture enables companies to develop purpose-built processors and microcontrollers internally without the need to pay royalties, making development of custom chips at a lower cost accessible to more companies. The RISC-V architecture license is available for free, and developers can either design their own core or choose an Open Source version. All told, RISC-V is supported by nearly 50 work groups, plus over 420 organizations, individuals, and universities that are members of the Switzerland-based, nonprofit RISC-V International group that officially oversees the RISC-V ISA. The organization is truly global, with 31 percent of its membership base in North America, 33 percent in Europe, and 37 percent in Asia-Pacific” according to the group’s website.

Who is adopting RISC-V?

As 2021 kicks into high gear, most major semiconductor manufacturers have are developing processor chips based on their own RISC-V core designs, and many are implementing cores targeting specific use cases and business models. Consequently, a robust startup ecosystem is evolving around the openness of RISC-V. For example, SiFive, the first fabless semiconductor company, which likens itself to a “Red Hat for Linux,” will soon release a RISC-V-based offering that includes pre-built, configurable cores. Others, like EdgeQ, are developing extensions to the baseline RISC-V ISA, with the addition of new instructions aimed at accelerating computationally expensive operations for applications such as AI and communications protocols.

Governments, too, are jumping on RISC-V. In addition to helping create the RISC-V instruction set at Berkeley back in 2010, DARPA has collaborated with the RISC-V Foundation for the past several years around security and other standards. RISC-V has also been selected as the baseline technology for processor development programs such as the European Processor Initiative, where the EU has designated RISC-V as the main footprint for semiconductor design.

With the heating up of global political and economic competition, RISC-V enables countries to collaborate, and not become reliant on a particular foreign supplier for processor technologies and manufactured chips. With RISC-V, each country can customize processors according to its particular requirements, although it may remain dependent on foreign technologies for chip-design software and manufacturing tools.

The Wall Street Journal recently reported that RISC-V activity is ramping up rapidly in China, in response to “competition among regional governments.” Additionally, Nikkei.com notes that RISC-V has been adopted by Chinese government-backed technology businesses in a bid to become more self-sufficient from the United States and EU, and reduce the country’s exposure to US export regulations that could also potentially restrict China companies’ access to both Arm and Intel architectures should the political climate worsen. The RISC-V foundation counts China’s Huawai as one of its founding members.

In the video below, RISC-V’s Calista Richmond gives a great overview of RISC-V technology from its start through its potential future, stepping through the benefits of an Open Source development model along with an open ISA.

RISC-V: The Open Era of Computing

Additional RISC-V background…

[ vws = 2 ]

Share your thoughts on this topic, below...